This invention generally relates to metallic electrodeposition and more particularly to a method of improving an electrodeposition process through use of a multi-electrode assembly allowing in-situ contact cleaning and reduction of particulate contamination in the electrolyte, the method and multi-electrode assembly particularly useful for semiconductor wafer electrodeposition processes.
In semiconductor fabrication, various layers of insulating material, semiconducting material and conducting material are formed to produce a multilayer semiconductor device. The layers are patterned to create features that taken together, form elements such as transistors, capacitors, and resistors. These elements are then interconnected to achieve a desired electrical function, thereby producing an integrated circuit (IC) device. The formation and patterning of the various device layers may be accomplished using various fabrication techniques including oxidation, implantation, deposition, epitaxial growth of silicon, lithography, etching, and planarization.
Sub-micron multi-level metallization is one of the key technologies for the next generation of ultra large scale integration (ULSI). The multilevel interconnects that lie at the heart of this technology require planarization of interconnect features formed in high aspect ratio apertures, including contacts, vias, metal interconnect lines and other features. Reliable formation of these interconnect features is very important to the success of ULSI and to the continued effort to increase circuit density and quality on individual substrates and die.
Copper and copper alloys have become the metal of choice for filling sub-micron, high aspect ratio interconnect features on semiconductor substrates. Copper and its alloys have lower resistivity and higher electromigration resistance compared to other metals such as, for example, aluminum. These characteristics are critical for achieving higher current densities increased device speed.
As circuit densities increase, the widths of vias, contacts, metal interconnect lines, and other features, decrease to sub-micron dimensions, whereas the thickness of the dielectric layers, through the use low-k (low dielectric constant) materials, has remained substantially constant. Consequently, the aspect ratios for the features, i.e., their height divided by width, has increased thereby creating additional challenges in adequately filling the sub-micron features with, for example, copper metal. Many traditional deposition processes such as chemical vapor deposition (CVD) have difficulty filling increasingly high aspect ratio features, for example, where the aspect ratio exceeds 2:1, and particularly where it exceeds 4:1.
As a result of these process limitations, electroplating or electrodeposition, which has previously been limited to the fabrication of patterns on circuit boards, is now emerging as a preferable method for filling metal interconnects structures such as via openings (holes) and trench line openings on semiconductor devices. Typically, electroplating uses a suspension of positively charged ions of deposition material, for example metal ions, in contact with a negatively charged substrate, as a source of electrons, to deposit (plate out) the metal ions onto the charged substrate, for example, a semiconductor wafer. A thin metal layer (seed layer) is first deposited on the semiconductor wafer and in etched features to provide an electrical path across the surfaces. An electrical current is supplied to the seed layer whereby the semiconductor wafer surface is electroplated with an appropriate metal, for example, aluminum or copper.
One exemplary process for forming a series of interconnected multiple layers, for example, is a damascene process. Although there are several different manufacturing methods for manufacturing damascene structures, all such methods employ a series of photolithographic masking and etching steps, typically by a reactive ion etch (RIE). In the typical multilayer semiconductor manufacturing process, for example, a series insulating layers are deposited to include a series of interconnecting metallization structures such as vias and metal line interconnects to electrically interconnect areas within the multilayer device and contact layers to interconnect the various devices on the chip surface. In most devices, pluralities of vias are separated from one another along the semiconductor wafer and selectively interconnect conductive regions between layers of a multi layer device. Metal interconnect lines typically serve to selectively interconnect conductive regions within a layer of a multilayer device. Vias and metal interconnect lines are selectively interconnected in order to form the necessary electrical connections.
In filling the via openings and trench line openings with metal, for example, copper, electroplating is a preferable method to achieve superior step coverage of sub-micron etched features. The method generally includes first depositing a barrier layer over the etched opening surfaces, such as via openings and trench line openings, depositing a metal seed layer, preferably copper, over the barrier layer, and then electroplating a metal, for example copper, over the seed layer to fill the etched features to form, for example, vias and trench lines. Finally, the deposited layers and the dielectric layers are planarized, for example, by chemical mechanical polishing (CMP), to define a conductive interconnect feature.
Metal electroplating (electrodeposition) in general is a well-known art and can be achieved by a variety of techniques. Common designs of cells for electroplating a metal on semiconductor wafers involve positioning the plating surface of the semiconductor wafer within an electrolyte solution including an anode with the electrolyte impinging perpendicularly on the plating surface. The plating surface is contacted with an electrical power source forming the cathode of the plating system such that ions in the plating solution deposit on the conductive portion of the plating surface.
For example, referring to FIG. 1A is shown a cross sectional representation of the relationship of an anode assembly 12 to a semiconductor wafer in a typical electroplating (electrodeposition). The anode assembly 12, includes an anode 14, for example, formed of copper or an alloy thereof for copper electroplating. The anode 14, is surrounded by a titanium top plate, 16A and a titanium bottom plate 16B. An anode pad 18 covers the titanium top plate for directing an electrolytic current flow indicated by directional arrows 20A to the semiconductor wafer 22 for electroplating, for example, copper, onto the semiconductor wafer surface 22A.
During the electroplating process the applied potential may be reversed in sign periodically during the deposition process causing an electropolishing process to occur at the semiconductor wafer surface 22A of already electrodeposited copper including at the electrical contacts (not shown) made to the wafer thereby cleaning the same.
Referring to FIG. 1B, upon changing the sign of the applied potential causing current reversal in the anode assembly 12, the current flow direction of the electrolyte, indicated for example by directional arrows 20B, carries the electrolyte, including for example, copper ions to make contact with the titanium plates, for example titanium top plate 16A, where it is electrodeposited for example, at top plate surface 17.
One problem with the prior art electrodeposition method is that the adhesion of differing metals, for example the copper plating on the titanium surface during current (electrical potential) reversal steps is poor. As a result, the copper plating will tend to peel after a time period becoming dislodged and accumulating in the electrolyte bath thereby producing defective electroplating coatings on the semiconductor wafer, for example, including electroplated copper particles. Further, the electroplating film uniformity suffers over time due to the particulate contamination. For example, referring to FIG. 2, the electroplating film thickness in thousands of Angstroms is represented on the vertical axis while a relative position on an electroplated film is represented on the horizontal axis. Line A represents an electroplating process carried out for about 180 seconds and line B represents an electroplating process carried for about 90 seconds. In comparison, line C represents the thickness of a seed layer. It is evident that the electroplating film represented by line A carried out for the longest period shows a greater variation in film thickness and consequently has poorer uniformity believed to be due to particulate contamination accumulation. Consequently, semiconductor wafer yield is reduced and throughput is reduced by the need for filtering maintenance of the electrolyte solution.
These and other shortcomings demonstrate a need in the semiconductor processing art to develop a method for electrodeposition whereby metal plating deposition on a dissimilar metal surface included in an anode is reduced or avoided thereby minimizing particulate contamination.
It is therefore an object of the invention to provide a method for electrodeposition whereby metal plating deposition on a dissimilar metal surface included in an anode is reduced or avoided thereby minimizing particulate contamination while overcoming other shortcomings and deficiencies in the prior art.
To achieve the foregoing and other objects, and in accordance with the purposes of the present invention, as embodied and broadly described herein, the present invention provides a method for improving a electrodeposited metal film uniformity and preventing metal deposition and peeling of deposited metal from an electrode during an electrodeposition and electropolishing process.
In a first embodiment according to the present invention, the method includes providing a first anode electrode assembly and a semiconductor wafer plating surface disposed in an electrolyte bath comprising a plating metal for deposition onto the semiconductor wafer plating surface; providing at least one additional anode electrode assembly comprising the plating metal disposed peripheral to the first anode electrode assembly for selectively applying the cathodic electrical potential during an electropolishing process; and, periodically alternating between an electrodeposition process and electropolishing process with respect to the semiconductor wafer plating surface such that the plating metal is preferentially plated onto the at least one additional electrode assembly.